SI5346A-B03246-GMR

Clock Generators, PLLs, Frequency Synthesizers Overview

The SI5346A-B03246-GMR is a dual DSPLL jitter attenuator featuring four inputs and four outputs in a 44-QFN package. It supports differential output frequencies up to 720 MHz and LVCMOS outputs up to 250 MHz. Input ranges include 8 kHz to 750 MHz for differential signals and 8 kHz to 250 MHz for LVCMOS. The device achieves ultra-low jitter of 95 fs rms (12 kHz–20 MHz). Operating temperatures range from –40 °C to +85 °C, with core voltages at VDD: 1.8 V ±5% and VDDA: 3.3 V ±5%.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Dual independent DSPLLs enable any-frequency conversion from any input source.
• Supports automatic and manual hitless input clock switching.
• Includes programmable holdover modes for frequency stability during input loss.
• Features glitchless on-the-fly frequency changes and DCO mode.

Clock Generators, PLLs, Frequency Synthesizers Applications

• OTN Muxponders and Transponders
• 10/40/100G network line cards
• GbE/10 GbE/100 GbE Synchronous Ethernet (ITU-T G.8262)
• Carrier Ethernet switches

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific ordering suffix against the manufacturer's current documentation to confirm tape-and-reel packaging and factory pre-programmed configuration details. Ensure compatibility with ClockBuilder Pro software settings for the designated numerical sequence ID.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this model for applications requiring two independent timing paths with low jitter performance. Verify that the required output frequency range fits within the 720 MHz differential or 250 MHz LVCMOS limits. Confirm input signal types match the supported differential or LVCMOS specifications.

Clock Generators, PLLs, Frequency Synthesizers Part Context

This component belongs to the Si5346 family, which offers dual DSPLL technology in a compact 44-QFN package. It serves as a lower-pin-count alternative to the quad-DSPLl Si5347, providing similar jitter attenuation capabilities for space-constrained designs.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

Si5346A-D-GM is a pin-compatible variant within the same series. Verify if the specific pre-programmed configuration matches requirements when substituting factory-programmed parts.

Clock Generators, PLLs, Frequency Synthesizers FAQ

What is the maximum differential output frequency?

The maximum differential output frequency is 720 MHz.

How does the device handle input clock failure?

It automatically enters Holdover Mode using stored historical frequency data to maintain output stability.

Can the device switch between gapped clocks?

Yes, it can lock to gapped clocks with missing periods, producing a periodic non-gapped output.