SI5380A-D08236-GM

Clock Generators, PLLs, Frequency Synthesizers Overview

The Skyworks SI5380A-D08236-GM is a high-performance, integer-based jitter attenuator and clock multiplier utilizing 4th generation DSPLL technology. It integrates frequency synthesis and jitter attenuation to eliminate external VCXO and loop filter components. The device features four inputs and twelve outputs in a 64-QFN package. Key electrical parameters include an ultra-low phase noise floor of -159 dBc/Hz and typical jitter of 65 fs (12 kHz to 20 MHz). Input frequencies range from 11.52 MHz to 737.28 MHz differentially, while outputs support up to 1.47456 GHz differentially. Supply voltages are 1.8 V ±5% for the core and 3.3 V ±5% for analog sections.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Integrates digital frequency synthesis and jitter attenuation using DSPLL technology to remove the need for external VCXOs and analog loop filters.
• Supports JESD204B clocking requirements including DCLK and SYSREF generation with configurable output formats such as LVDS, LVPECL, and LVCMOS.
• Provides hitless input switching between frequency-locked sources and glitchless switching for asynchronous inputs to prevent output transients.

Clock Generators, PLLs, Frequency Synthesizers Applications

• JESD204B clock generation for data converters
• Remote Radio Units (RRU) and Remote Radio Heads (RRH)
• Wireless base stations supporting 3G, GSM, W-CDMA, 4G/LTE, and LTE-A standards

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific ordering suffix against the manufacturer's current documentation to confirm configuration details. Note that this component is designated as Not Recommended for New Designs by Skyworks Solutions Inc., which may impact long-term availability and support. Ensure compatibility with existing system designs before procurement.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this component for applications requiring ultra-low phase noise and high integration levels in wireless infrastructure. Verify that the required output frequencies fall within the specified differential and LVCMOS ranges. Confirm that the serial interface configuration meets the system's control requirements and that the operating temperature range aligns with the environmental conditions.

Clock Generators, PLLs, Frequency Synthesizers Part Context

This part belongs to the Si5380 family of wireless jitter attenuators and clock multipliers. It is designed for small cell and base station applications demanding high performance. The 'GM' suffix indicates a lead-free, RoHS-6 compliant 64-QFN package. The numerical suffix represents a factory pre-programmed configuration assigned via ClockBuilder Pro software.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

Public confirmed substitute part numbers are not available in the provided datasheet. As the device is marked Not Recommended for New Designs, alternative solutions should be evaluated based on specific jitter and frequency requirements.