SI5381A-C-GMR

Clock Generators, PLLs, Frequency Synthesizers Overview

The Si5381A-C-GMR is a multi-DSPLL wireless jitter attenuator and clock multiplier from Skyworks Solutions. It integrates four digital synthesizer phase-locked loops (DSPLLs) in a single chip, replacing discrete VCXO-based solutions. The device supports simultaneous Ethernet, CPRI, and general-purpose clocking with ultra-low noise performance. Key electrical parameters include an input frequency range of 8 kHz to 750 MHz for differential inputs and 8 kHz to 250 MHz for LVCMOS inputs. Output frequencies reach up to 2.94912 GHz for CPRI applications via DSPLL_B and up to 735 MHz for other differential outputs. The device features 4 inputs and 12 outputs, operates on a 1.8 V core voltage, and functions within a temperature range of -40°C to +85°C.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Integrates multiple DSPLLs to eliminate external VCXOs and analog loop filters
• Supports simultaneous Ethernet, CPRI, and general-purpose clock generation
• Provides hitless and glitchless input switching capabilities
• Includes automatic free-run and holdover modes for signal continuity

Clock Generators, PLLs, Frequency Synthesizers Applications

• Wireless Infrastructure Baseband Units (BBU)
• Distribution Units (DU) in cellular networks
• eCPRI Remote Radio Heads (RRH)
• Test and Measurement equipment requiring low-jitter clocks

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific ordering suffix against the manufacturer's current datasheet revision. Suffixes often indicate package type, tape-and-reel options, or factory pre-programmed configurations. Confirm that the requested part number matches the exact functional requirements and pinout compatibility before finalizing procurement orders.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this component when designing systems requiring combined CPRI and Ethernet clock distribution. Ensure the design accommodates the required 54 MHz external reference oscillator. Verify that the output format requirements (LVDS, LVPECL, LVCMOS, CML, HCSL) align with the load specifications of the destination devices.

Clock Generators, PLLs, Frequency Synthesizers Part Context

This device belongs to the Si538x family of high-performance clock multipliers. It is designed to supersede traditional analog jitter cleaner architectures by providing a fully integrated digital solution. The Si5381 variant specifically offers four DSPLLs and twelve outputs, distinguishing it from lower-output variants within the same product line.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

Direct replacements include other SKUs within the Si5381A-E series, such as Si5381A-E-GM or Si5381A-E-GMR, depending on packaging preferences. Factory pre-programmed versions may require specific ordering codes generated via ClockBuilder Pro software.