SY89828LHI

Clock Buffers, Drivers Overview

The SY89828LHI is a dual 1:10 LVDS fanout buffer and translator manufactured by Micrel, Inc. It operates on a single 3.3V supply and provides two banks of ten differential LVDS outputs. The device features a 2:1 input multiplexer for each bank, accepting either LVDS or LVPECL signals. Key electrical specifications include a maximum toggle frequency (fMAX) of 1.0 GHz, within-device skew under 50 ps, cycle-to-cycle jitter below 1 ps RMS, and total peak-to-peak jitter under 1 ps. Propagation delay ranges from 0.8 ns to 1.6 ns depending on the input type and amplitude.

Clock Buffers, Drivers Feature Summary

• Dual 1:10 architecture with independent 2:1 input muxes per bank
• Low skew (<50ps) and ultra-low jitter (<1ps RMS cycle-to-cycle)
• Synchronous output enable function prevents runt clock pulses
• Internal 100Ω termination for LVDS inputs

Clock Buffers, Drivers Applications

• Enterprise networking equipment
• High-end server systems
• Redundant clock switchover circuits

Clock Buffers, Drivers Procurement Notes

Verify component authenticity through authorized channels as this part was originally produced by Micrel, Inc. before its acquisition by Microchip Technology. Confirm that the specific ordering suffix matches the required lead finish (Sn-Pb or Matte-Sn). Ensure PCB design accommodates the exposed pad thermal requirements for the H64-1 package.

Clock Buffers, Drivers Selection Notes

Select the SY89828LHI when a high-density 20-output LVDS distribution solution is required with precise timing alignment. This model supports both LVDS and LVPECL inputs via internal multiplexing, eliminating the need for external level shifters. Verify that the application environment remains within the industrial temperature range (-40°C to +85°C) specified for this variant.

Clock Buffers, Drivers Part Context

This component belongs to the Precision Edge series of high-performance clock buffers. Originally developed by Micrel, Inc., it serves as a specialized interface for translating and distributing low-voltage differential signals in high-speed digital systems requiring minimal phase noise and skew across multiple loads.

Clock Buffers, Drivers Replacement Considerations

Publicly confirmed substitute part numbers are not available in the provided documentation. Designers should consult current Microchip Technology product portfolios for modern equivalents if new procurement is required.

Clock Buffers, Drivers FAQ

How does the synchronous output enable prevent glitches?

The OE1 and OE2 inputs disable the outputs only when they are already in the LOW state. This synchronization prevents the generation of runt clock pulses that can occur with asynchronous control during enable/disable transitions.

What is the difference between LVDS and LVPECL input handling?

LVDS inputs (LVDS_CLKA/B) have an internal 100Ω termination resistor. LVPECL inputs (LVPECL_CLKA/B) require external termination and utilize internal 75kΩ pull-down resistors when not selected.

What happens to unused output pairs?

Unused output pairs must be terminated with a 100Ω resistor to maintain low jitter and skew performance. When disabled, Q outputs remain static LOW and /Q outputs remain static HIGH.