Flip Flops 74AUP2G79GD,125 product image

74AUP2G79GD,125

$0.13
  • Description:IC FF D-TYPE DUAL 1BIT 8XSON
  • Series:74AUP
  • Mfr:Nexperia USA Inc.
  • Package:Bulk

SKU:6f180fa69c8a Category: Brand:

  
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74AUP2G79GD,125 is listed in the Flip Flops range at ChipApex. The manufacturer field lists Nexperia USA Inc.. Its product description is IC FF D-TYPE DUAL 1BIT 8XSON. Review the specifications below when checking this part for your BOM.

Flip Flops specifications for 74AUP2G79GD,125

  • Description:IC FF D-TYPE DUAL 1BIT 8XSON
  • Series:74AUP
  • Mfr:Nexperia USA Inc.
  • Package:Bulk
  • Function:Standard
  • Type:D-Type
  • Output Type:Non-Inverted
  • Number of Elements:2
  • Number of Bits per Element:1
  • Clock Frequency:309 MHz
  • Max Propagation Delay @ V, Max CL:5.8ns @ 3.3V, 30pF
  • Trigger Type:Positive Edge
  • Current - Output High, Low:4mA, 4mA
  • Voltage - Supply:0.8V ~ 3.6V
  • Current - Quiescent (Iq):500 nA
  • Operating Temperature:-40°C ~ 125°C (TA)
  • Mounting Type:Surface Mount
  • Supplier Device Package:8-XSON (2x3)
  • Package / Case:8-XFDFN
  • Input Capacitance:0.6 pF
  • Grade:-
  • Qualification:-

Flip Flops datasheet and documents for 74AUP2G79GD,125

74AUP2G79GD,125

Flip Flops Overview

The 74AUP2G79GD,125 is a dual D-type flip-flop from the Nexperia AUP series, housed in an 8-XFDFN package. It features positive-edge triggering and non-inverting outputs. The device operates within a supply voltage range of 0.8 V to 3.6 V, with a maximum propagation delay of 14.2 ns and a clock frequency up to 309 MHz. It supports partial power-down via I_OFF circuitry and complies with JEDEC standards for various voltage levels.

Flip Flops Feature Summary

  • Dual D-type flip-flops with positive-edge triggering
  • I_OFF circuitry enables partial power-down mode operation
  • Overvoltage tolerant inputs up to 3.6 V
  • Compliant with JEDEC low-voltage standards

Flip Flops Applications

  • Portable battery-powered equipment
  • Partial power-down applications
  • Low-voltage logic systems

Flip Flops Procurement Notes

Verify the specific package variant against project requirements, as the GD suffix indicates an XFDFN package distinct from other versions like DC (VSSOP). Confirm that the 309 MHz specification aligns with system timing constraints. Ensure compatibility with the required operating temperature range and JEDEC compliance standards before finalizing component selection.

Flip Flops Selection Notes

Select this component for designs requiring dual flip-flops in a compact footprint with low power consumption. The wide supply voltage range suits multi-voltage domains. Verify that the XFDFN package is suitable for the assembly process. Consider the I_OFF feature if the design requires preventing backflow current during power-down states.

Flip Flops Part Context

This part belongs to the 74AUP family of advanced ultra-low-power CMOS logic devices. It is designed for applications demanding high speed and minimal energy usage. The AUP series is characterized by its ability to operate at low voltages while maintaining robust noise immunity and fast switching speeds compared to standard logic families.

Flip Flops Replacement Considerations

The 74AUP2G79DC-Q100H is a qualified automotive alternative in a different package. The 74AUP2G79GD,125 is the primary equivalent in the same package family.

74AUP2G79GD,12574AUP2G79GD,125
$0.13
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