AD9152BCPZ

Overview

The AD9152BCPZ is a dual, 16-bit high dynamic range digital-to-analog converter (DAC) from the TxDAC+ family. It supports a maximum DAC update rate of 2.25 GSPS with 2×, 4×, or 8× interpolation filters. The device features a flexible four-lane JESD204B interface supporting lane rates up to 12.38 Gbps and includes an integrated low-noise PLL clock multiplier. Key specifications include ±10 LSB INL, programmable full-scale output current from 4 mA to 20 mA, and power consumption of 1223 mW at 1.5 GSPS. It operates within an industrial temperature range of −40°C to +85°C in a 56-lead LFCSP package.

Feature Summary

• Dual-channel 16-bit architecture with 2.25 GSPS maximum sample rate
• Four-lane JESD204B Subclass 1 serial interface for deterministic latency
• Integrated low-noise PLL clock multiplier with internal 0.5 V reference
• Programmable transmit enable function for power optimization

Applications

• Multicarrier LTE and GSM base stations
• Software defined radios
• Wideband repeaters and point-to-point microwave radios
• Automated test equipment

Procurement Notes

Verify the specific suffix 'BCPZ' against the manufacturer's ordering guide to confirm package type and temperature grade. Ensure that the required supply voltages (AVDD33, PVDD12, DVDD12, etc.) are correctly decoupled according to the datasheet recommendations. Confirm that the PCB layout accommodates the 56-lead LFCSP footprint with an exposed pad connected to ground for thermal management.

Selection Notes

Select this component when designing systems requiring high linearity and wide bandwidth for multiband wireless applications. The AD9152 is optimized for seamless interfacing with Analog Devices analog quadrature modulators like the ADRF6720. Consider the fixed latency characteristics and JESD204B link configuration requirements during system synchronization planning.

Part Context

The AD9152 belongs to the TxDAC+ family of high-performance DACs. It is designed to support input data rates up to 1.125 GSPS while delivering ultrawide signal bandwidth. The device integrates digital signal processing blocks such as inverse sinc filtering and programmable FIR filters to enhance signal quality before conversion.

Replacement Considerations

Public confirmed substitute part numbers: None.