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SI5345A-B04804-GM is listed in the Clock Generators, PLLs, Frequency Synthesizers range at ChipApex. The manufacturer field lists Skyworks Solutions Inc.. Its product description is IC CLK MULTIPLIER ATTENUATOR. Review the specifications below when checking this part for your BOM.
The Skyworks SI5345A-B04804-GM is a low-jitter, 10-output clock synthesizer and jitter attenuator. It utilizes fourth-generation DSPLL and MultiSynth technologies to generate any combination of output frequencies from any input frequency. The device supports differential inputs from 8 kHz to 750 MHz and LVCMOS inputs up to 250 MHz. Output frequencies range from 100 Hz to 1028 MHz for differential outputs and up to 250 MHz for LVCMOS. It features ultra-low jitter performance of 90 fs rms and meets ITU-T G.8262 EEC Option 1 and 2 standards. The component operates on a single 1.8 V core voltage and includes in-circuit programmable non-volatile memory.
Verify the specific factory preprogrammed configuration associated with the B04804 suffix against the required system specifications. Confirm that the QFN-64 package dimensions match the PCB land pattern requirements. Ensure compatibility with the I2C or SPI serial interface used by the host controller for initialization and monitoring.
Select this model when high-frequency outputs up to 1028 MHz are required alongside low-jitter performance. The Si5345A variant supports both integer and fractional synthesis modes, offering greater flexibility than integer-only versions. Verify that the application requires ten independent output channels and four input options for redundancy or synchronization.
This component belongs to the Si5345 family, which also includes the Si5344 (4 outputs) and Si5342 (2 outputs). All variants share similar internal architectures and feature sets but differ in pin count and output capacity. The Si5345A specifically denotes the high-performance version capable of generating frequencies up to 1028 MHz with full fractional synthesis capabilities.
Si5345A-D-GMR
The Si5345A supports differential output frequencies up to 1028 MHz and LVCMOS output frequencies up to 250 MHz.
Yes, the DSPLL can lock to gapped input clocks provided the minimum frequency is 10 MHz with no more than two missing cycles out of every eight.
The loop bandwidth is digitally programmable via the serial interface, allowing settings between 0.1 Hz and 4 kHz for optimization of jitter performance.
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