SI5345D-D-GM

Clock Generators, PLLs, Frequency Synthesizers Overview

The SI5345D-D-GM is a jitter attenuator and clock multiplier featuring four inputs and ten outputs in a 64-QFN package. It supports differential input frequencies from 8 kHz to 750 MHz and LVCMOS inputs up to 250 MHz. Output frequencies range from 100 Hz to 350 MHz for differential signals and up to 250 MHz for LVCMOS. The device operates on a 1.71 V to 3.47 V supply, achieves ultra-low jitter of 90 fs rms, and functions within a temperature range of -40°C to +85°C.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Generates any combination of output frequencies from any input frequency using fourth-generation DSPLL and MultiSynth technologies.
• Supports free-run, synchronous, and holdover modes with automatic or manual hitless input clock switching.
• Features fully integrated loop filter and digitally programmable jitter attenuation bandwidth for optimized performance.
• Includes in-circuit programmable non-volatile memory to ensure known frequency configuration upon power-up.

Clock Generators, PLLs, Frequency Synthesizers Applications

• OTN muxponders and transponders
• 10/40/100 G networking line cards
• GbE/10 GbE/100 GbE Synchronous Ethernet (ITU-T G.8262)
• Carrier Ethernet switches
• SONET/SDH line cards

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific ordering suffix against the manufacturer's current documentation to confirm package type and programming status. Factory preprogrammed devices require unique part numbers assigned by Skyworks. Confirm availability through authorized distributors as standard lead times may vary based on production schedules.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select the SI5345D variant when the application requires output frequencies up to 350 MHz. Use ClockBuilder Pro software to configure the serial interface settings and generate the necessary NVM data. Ensure the external crystal frequency falls between 25 MHz and 54 MHz for optimal jitter performance and stability during free-run or holdover modes.

Clock Generators, PLLs, Frequency Synthesizers Part Context

This component belongs to the Si5345/44/42 Rev D family of jitter attenuators. The 'D' suffix indicates support for output frequencies up to 350 MHz, distinguishing it from the 'A' and 'C' variants which support higher frequencies up to 1028 MHz. The 'GM' suffix denotes the 64-QFN package format.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

SI5345A-D-GM: Supports higher output frequencies up to 1028 MHz.

Clock Generators, PLLs, Frequency Synthesizers FAQ

How does the device handle input clock failure?

The device automatically enters holdover mode if the selected input clock becomes invalid and no other valid inputs are available, using stored historical frequency data to minimize phase disturbance.

What is the purpose of the Fastlock feature?

Fastlock allows the DSPLL to acquire lock faster by temporarily using a higher loop bandwidth during the acquisition process before reverting to the normal low bandwidth setting.

Can the device switch between gapped clock inputs?

Yes, the DSPLL supports locking to gapped clocks with missing periods, producing a periodic non-gapped output clock with an average frequency of the input.