SI5348B-B-GMR

Clock Generators, PLLs, Frequency Synthesizers Overview

The Skyworks SI5348B-B-GMR is a network synchronizer and jitter attenuator featuring three independent DSPLLs in a 64-lead QFN package. It supports SyncE, IEEE 1588 PTP, and SETS architectures with ultra-low jitter of 95 fs (12 kHz to 20 MHz). The device accepts differential inputs from 8 kHz to 750 MHz and LVCMOS inputs up to 250 MHz. Differential outputs range from 1 PPS to 350 MHz, while LVCMOS outputs reach 250 MHz. Operating voltages include VDD at 1.8 V ±5% and VDDA at 3.3 V ±5%. It functions within a temperature range of –40 °C to +85 °C.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Three independent DSPLLs supporting flexible SyncE/IEEE 1588 and SETS architectures
• Enhanced hitless switching minimizes output phase transients during input changes
• Pin or software controllable DCO mode provides precise timing adjustment for clock steering
• Programmable jitter attenuation bandwidth per DSPLL allows customized loop filtering

Clock Generators, PLLs, Frequency Synthesizers Applications

• Synchronous Ethernet (SyncE) ITU-T G.8262 EEC Option 1 & 2
• Telecom Boundary Clock (T-BC) as defined by ITU-T G.8273.2
• IEEE 1588 (PTP) slave clock synchronization
• Stratum 3/3E, G.812, G.813 network synchronization

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific ordering suffix against the manufacturer's current documentation to confirm package type and tape/reel configuration. Ensure compatibility with ClockBuilder Pro software versions for accurate pre-programming. Confirm RoHS-6 compliance status and lead-free specifications prior to finalizing procurement orders.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this model when applications require three independent PLLs for complex synchronization topologies. Verify that the required output frequency range does not exceed 350 MHz for differential signals. Ensure the design accommodates external TCXO or OCXO references for holdover stability. Check serial interface requirements for I2C or SPI control compatibility.

Clock Generators, PLLs, Frequency Synthesizers Part Context

This component belongs to the Si5348 family of packet network synchronizers designed for telecom and data center timing. It integrates DSPLL technology to provide low-jitter performance in a compact footprint. The B-grade designation indicates a maximum output frequency limit compared to higher-performance variants within the same series.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation.