SI5368A-C-GQ

Clock Generators, PLLs, Frequency Synthesizers Overview

The Si5368A-C-GQ is a jitter-attenuating precision clock multiplier utilizing third-generation DSPLL technology. It accepts four differential or single-ended clock inputs from 2 kHz to 710 MHz and generates five outputs ranging from 2 kHz to 945 MHz, with select frequencies reaching 1.4 GHz. The device operates on a single supply voltage of 1.8 V, 2.5 V, or 3.3 V within an ambient temperature range of -40°C to 85°C. It features an integrated loop filter with digitally programmable bandwidth from 60 Hz to 8.4 kHz. Configuration is managed via I2C or SPI interfaces, supporting manual or automatic hitless switching between input sources.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Generates any frequency translation combination across the operating range using independent dividers for each input and output clock.
• Provides ultra-low jitter performance with generation as low as 300 fs rms in the 12 kHz–20 MHz band.
• Supports manual or automatically controlled hitless switching and phase build-out among four clock inputs.
• Includes SONET frame sync switching, regeneration, and support for ITU G.709 and custom FEC ratios.

Clock Generators, PLLs, Frequency Synthesizers Applications

• SONET/SDH OC-48/STM-16/OC-192/STM-64 line cards
• GbE/10GbE, 1/2/4/8/10/16G Fibre Channel systems
• ITU G.709 and custom FEC line cards
• Wireless basestations
• Data converter clocking

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific ordering suffix against the manufacturer's official documentation to confirm package type, temperature grade, and control interface settings. Ensure that the selected configuration complies with power dissipation limits when operating at 3.3 V with multiple LVPECL or CMOS outputs enabled. Cross-reference the part number with the latest Skyworks Solutions datasheet to validate current production status and environmental compliance requirements.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this component for applications requiring sub 1 ps rms jitter performance and flexible frequency synthesis. Evaluate the required output signal formats (LVPECL, LVDS, CML, CMOS) to ensure compatibility with downstream circuitry and power constraints. Utilize the DSPLLsim software utility to optimize PLL divider settings for minimal phase noise and power consumption based on specific input and output frequency combinations.

Clock Generators, PLLs, Frequency Synthesizers Part Context

The Si5368 belongs to the Skyworks Solutions Si53xx family of timing devices, which are designed for high-performance clock multiplication and jitter attenuation. This series leverages proprietary DSPLL technology to eliminate external components typically required in traditional PLL solutions. The Si5368 variant specifically targets complex telecommunications and data communication environments demanding precise clock distribution and synchronization capabilities.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

Public confirmed substitute part numbers: SI5368B-B-GQ, SI5368A-B-GQ.

Clock Generators, PLLs, Frequency Synthesizers FAQ

What is the maximum output frequency supported by the Si5368?

The Si5368 generates outputs ranging from 2 kHz to 945 MHz generally, with select frequencies capable of reaching up to 1.4 GHz.

How is the loop filter configured in the Si5368?

The Si5368 features an integrated loop filter with a digitally programmable selectable loop bandwidth ranging from 60 Hz to 8.4 kHz.

Can the Si5368 switch between input clocks without interruption?

Yes, the device supports manual or automatically controlled hitless switching and phase build-out among its four clock inputs.