SI5381E-E-GMR

Clock Generators, PLLs, Frequency Synthesizers Overview

The SI5381E-E-GMR is a discontinued ultra-low phase noise, dual-PLL wireless jitter attenuating clock multiplier from the Si538x series. It features 4 inputs and 12 outputs with a maximum output frequency of 2.94912 GHz and a maximum input frequency of 750 MHz. The device operates on a single supply voltage ranging from 1.71 V to 1.89 V, consuming 175 mA of current with a power dissipation of 1.125 W. It supports CML, HCSL, LVCMOS, LVDS, and LVPECL output levels and accepts differential or LVCMOS input levels. Packaged in a QFN-64 format, it functions within an operating temperature range of -40°C to +85°C.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Integrates dual independent any-frequency DSPLLs for flexible timing path generation
• Supports automatic and hitless input clock switching with holdover modes
• Provides immunity to external noise coupling from power supplies via fourth-generation DSPLL technology
• Features programmable loop bandwidth settings for configurable jitter attenuation

Clock Generators, PLLs, Frequency Synthesizers Applications

• Ultra-low phase noise 4G/LTE clock generation
• Low jitter general-purpose clock synthesis
• JESD204B Subclass 0 and Subclass 1 clocking for ADCs and DACs

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify component status as this specific part number is marked as obsolete and no longer manufactured. Confirm availability of direct replacement options such as the SI5381A-E-GMR through authorized distributors. Ensure that ordering suffixes do not imply functional changes unless explicitly documented by the manufacturer. Request updated lifecycle notifications to manage long-term supply risks effectively.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this component only if legacy compatibility with the Rev E silicon is required. Evaluate the SI5381A-E-GMR as the primary alternative for new designs due to current production status. Verify that the QFN-64 package footprint matches the PCB layout constraints. Confirm that the 1.71 V to 1.89 V supply range aligns with the system power architecture requirements.

Clock Generators, PLLs, Frequency Synthesizers Part Context

This device belongs to the Skyworks Si538x family of clock multipliers designed for wireless and wireline applications. It utilizes fourth-generation DSPLL technology to provide any-frequency conversion capabilities. The family integrates multiple PLLs to support complex timing trees while maintaining low jitter performance suitable for high-speed data converters and base station infrastructure.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

The SI5381A-E-GMR is listed as a direct substitute for the SI5381E-E-GMR. Verify pinout and register compatibility before transitioning designs. Review the device errata for both revisions to identify any functional differences or known limitations.