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24LC128T-I/ST is listed in the Memory IC range at ChipApex. The manufacturer field lists Microchip Technology. Its product description is IC EEPROM 128KBIT I2C 8TSSOP. Review the specifications below when checking this part for your BOM.
The Microchip Technology 24LC128T-I/ST is a 16K x 8 (128 Kbit) Serial Electrically Erasable PROM (EEPROM). It operates with a single supply voltage ranging from 2.5V to 5.5V and features an I2C compatible two-wire serial interface supporting up to 400 kHz clock frequency at VCC ≥ 2.5V. The device includes a 64-byte page write buffer, hardware write-protect capability via the WP pin, and Schmitt trigger inputs for noise suppression. It supports random and sequential reads across the full memory boundary.
Verify the specific suffix 'I/ST' corresponds to Industrial temperature range (-40°C to +85°C) and TSSOP-8 packaging. Confirm RoHS compliance status as required by project specifications. Ensure the design accounts for the 2.5V minimum operating voltage characteristic of the LC series compared to other variants in the family.
Select this component when a 128 Kbit EEPROM with I2C interface is required within the 2.5V to 5.5V voltage range. Choose this part over the 24AA128 if operation below 2.5V is not needed, or over the 24FC128 if 1 MHz speed is unnecessary. Consider the TSSOP-8 package constraints for PCB layout and thermal management requirements.
This device belongs to the 24XX128 family, which also includes the 24AA128 and 24FC128. While sharing identical memory architecture and interface protocols, the 24LC128 is distinguished by its 2.5V minimum operating voltage limit, whereas the AA and FC variants support operation down to 1.7V. The 'T' indicates tape and reel packaging, and 'ST' denotes the TSSOP-8 package type.
24LC128-I/ST
Up to eight 24LC128 devices can be connected to the same bus by configuring the A0, A1, and A2 address pins to different logic levels.
The Write-Protect (WP) pin allows hardware protection of the entire memory array. When tied to VCC, write operations are inhibited; when tied to VSS, writes are enabled.
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