AD9680BCPZ-1250

Analog To Digital Converters (ADC) Overview

The AD9680BCPZ-1250 is a dual-channel, 14-bit analog-to-digital converter (ADC) operating at a maximum sampling rate of 1.25 GSPS. It features a pipelined architecture with integrated buffers and sample-and-hold circuits. The device provides JESD204B Subclass 1 serial digital outputs and includes two integrated wideband digital downconverters (DDCs) per channel. Key electrical specifications include a full power bandwidth of 2 GHz, an SNR of 63.6 dBFS at 10 MHz input frequency, and an SFDR of 84 dBFS at 10 MHz. It operates on 1.25 V, 2.5 V, and 3.3 V supplies within the -40°C to +85°C temperature range.

Analog To Digital Converters (ADC) Feature Summary

• Integrated dual-channel ADC cores with multistage differential pipelined architecture and output error correction logic.
• On-chip buffer and sample-and-hold circuit designed for low power consumption and ease of use.
• Two integrated wideband digital processors per channel featuring a 12-bit NCO and up to four half-band filters.
• Flexible JESD204B lane configurations supporting one, two, or four-lane setups for high-speed serialized data output.

Analog To Digital Converters (ADC) Applications

• Communications diversity multiband and multimode digital receivers
• General-purpose software radios
• Ultrawideband satellite receivers
• Radar systems
• Signals intelligence (SIGINT)

Analog To Digital Converters (ADC) Procurement Notes

Verify the specific speed grade suffix matches the required sampling rate. Confirm package type and RoHS compliance against the manufacturer's current ordering guide. Ensure environmental ratings align with operational requirements.

Analog To Digital Converters (ADC) Selection Notes

Select based on required sampling rate and input bandwidth. Evaluate power consumption constraints against available supply rails. Consider DDC configuration needs for signal processing complexity and lane rate limitations of the receiving logic.

Analog To Digital Converters (ADC) Part Context

This component belongs to the AD9680 family of high-speed dual ADCs from Analog Devices. The family includes variants optimized for different sampling rates, such as 1 GSPS, 820 MSPS, and 500 MSPS, sharing common architectural features and pinouts.

Analog To Digital Converters (ADC) Replacement Considerations

Check for AD9680BCPZRL7-1000 for lower sampling rate applications. Verify compatibility with AD9691BCPZ-1250 if higher resolution or different interface requirements are needed.

Analog To Digital Converters (ADC) FAQ

What is the nominal differential input voltage range for the AD9680-1250?

The nominal differential input voltage range for the AD9680-1250 is 1.58 V p-p.

Does the AD9680 support deterministic latency?

Yes, the device supports deterministic latency through JESD204B Subclass 1 operation, allowing for precise synchronization between multiple devices using SYSREF± inputs.

How many lanes can the JESD204B interface be configured for?

The JESD204B interface supports flexible lane configurations, including one, two, or four lanes, depending on the DDC configuration and acceptable lane rate.