PI6C39911-2JE

Clock Generators, PLLs, Frequency Synthesizers Overview

The PI6C39911-2JE is a programmable skew zero-delay clock buffer manufactured by Diodes Incorporated. It operates on a single 3.3V supply and features four pairs of user-controllable outputs capable of driving 50-Ohm terminated lines. The device supports input frequencies from 3.125 MHz to 133 MHz and output frequencies from 12.5 MHz to 133 MHz. Key electrical parameters include typical output pair skew less than 100ps, jitter below 200ps peak-to-peak, and propagation delay ranging from 0.3ns to 0.7ns depending on the frequency select setting. It utilizes a 32-pin PLCC package.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Provides selectable control over system clock functions with up to ±12 time units of output-to-output skew capability.
• Integrates a Phase Locked Loop (PLL) that cancels external load and transmission line delay effects for zero input-to-output delay.
• Supports divide-by-two and divide-by-four output functions for flexible clock distribution and multiplication.
• Features inputs tolerant to 5V levels while operating from a single 3.3V supply.

Clock Generators, PLLs, Frequency Synthesizers Applications

• Zero-skew clock distribution trees in high-performance computer systems.
• Equalizing skew between metal traces of varying lengths on printed circuit boards.
• Clock multiplier configurations using divided outputs fed back to the feedback pin.
• Board-to-board clock distribution where cascaded buffers compensate for wire delays.

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify component authenticity through authorized distributors or direct manufacturer channels. Confirm RoHS compliance status and lead-free packaging details as specified in the ordering information. Ensure the specific suffix matches the required tape and reel or tube packaging configuration before finalizing procurement orders.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this component when designing complex clock systems requiring precise phase alignment and low skew across multiple loads. Consider the FS pin configuration to match the desired operating frequency range. Evaluate the need for inverted or divided outputs to determine appropriate strapping of function select inputs relative to the feedback path.

Clock Generators, PLLs, Frequency Synthesizers Part Context

This part belongs to the SuperClock family of programmable skew clock drivers. It is designed to optimize timing in high-speed digital systems by providing configurable output delays and frequency division capabilities within a single integrated circuit package.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

No public confirmed substitute part numbers are available in the provided documentation. Verify pin compatibility and electrical specifications if considering alternative vendors.

Clock Generators, PLLs, Frequency Synthesizers FAQ

How is the operating frequency range selected?

The operating frequency range is selected by connecting the FS pin to HIGH, MID, or LOW states, which corresponds to different frequency bands such as 15-30 MHz, 31-60 MHz, or 61-133 MHz.

What is the maximum skew capability between outputs?

Outputs can be skewed up to ±6 time units from their nominal zero skew position, allowing for a total output-to-output skew range of up to ±12 time units.

Can the device function without the internal PLL?

Yes, by forcing the TEST input to its MID or HIGH state, the internal PLL disconnects, and inputs supplied to REF directly control all outputs while maintaining relative output-to-output functions.