PI6CBE33045ZHIEX-13R

Clock Buffers, Drivers Overview

The PI6CBE33045 is a low-power, four-output zero-delay buffer (ZDB) and fanout clock buffer designed for PCIe 1.0 through 6.0 and UPI applications. It accepts a differential HCSL input and provides four differential HCSL outputs with integrated 85Ω on-chip termination. The device features a proprietary PLL to achieve very low jitter, supporting selectable bandwidths and spread spectrum tolerance. It operates at a core supply voltage of 3.3V and supports hardware or SMBus control for mode selection and individual output enables.

Clock Buffers, Drivers Feature Summary

• Four differential low-power HCSL outputs with default 85Ω on-chip termination
• Supports Zero-Delay Buffer (ZDB) and Fanout Buffer modes via hardware or SMBus
• Very low jitter performance: <50ps cycle-to-cycle; additive phase jitter as low as 0.012 ps RMS for PCIe 6.0
• Spread spectrum tolerant with selectable PLL bandwidths (Low/High/Bypass)
• Individual active-low output enable pins (OE0#-OE3#) for power management

Clock Buffers, Drivers Applications

• PCIe 1.0/2.0/3.0/4.0/5.0/6.0 clock distribution
• UPI (Ultra Path Interconnect) clock buffering
• QPI/UPI clock generation systems
• DB2000Q compatible clock networks

Clock Buffers, Drivers Procurement Notes

Verify the ordering suffix 'X' indicates tape and reel packaging and '-13R' specifies top-left corner pin 1 orientation. Confirm the 'I' suffix denotes industrial temperature range (-40°C to +85°C). Ensure the 'E' suffix confirms lead-free and green status. Check current availability as component status may change.

Clock Buffers, Drivers Selection Notes

Select this component when driving multiple high-speed serial links requiring low skew and jitter. Use ZDB mode for minimal propagation delay in common-clocked architectures. Use Fanout mode for SRIS architectures. Ensure input clock frequency is within 1-400 MHz. Verify 3.3V supply compatibility and SMBus interface requirements for configuration.

Clock Buffers, Drivers Part Context

This part belongs to Diodes Incorporated's PI6CBE33xx series of low-power clock buffers. It is specifically optimized for next-generation interconnect standards like PCIe 6.0 and UPI, offering improved jitter performance over previous generations while maintaining compatibility with legacy PCIe standards.

Clock Buffers, Drivers Replacement Considerations

Direct replacements within the same family include PI6CBE3308x and PI6CBE3306x, though these have different output counts and fixed SMBus addresses. Cross-family comparisons should consider output count, package type, and specific jitter specifications for the target application speed.

Clock Buffers, Drivers FAQ

What is the maximum input frequency supported by the PI6CBE33045?

The device supports an input frequency range from 1 MHz to 400 MHz.

How is the SMBus address configured?

The SMBus address is latched based on the logic levels applied to the SADR0_tri and SADR1_tri pins during startup. For the PI6CBE33045, the base address is D8h, but it can be modified using these tri-level latch pins.

Does the device support Spread Spectrum Clocking (SSC)?

Yes, the PI6CBE33045 is spread spectrum tolerant. It allows for triangular modulation frequencies between 30 kHz and 33 kHz for PCIe applications.