SI5345D-B04128-GMR

Clock Generators, PLLs, Frequency Synthesizers Overview

The SI5345D-B04128-GMR is a jitter attenuator and clock multiplier from the Si5345 family, featuring four inputs and ten outputs in a 64-QFN package. It supports differential input frequencies from 8 kHz to 750 MHz and LVCMOS inputs up to 250 MHz. The device generates any output frequency from 100 Hz to 350 MHz with ultra-low jitter of 90 fs rms. Operating voltages include VDD at 1.8 V ±5% and VDDA at 3.3 V ±5%. It functions within a temperature range of –40 to +85 °C.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Generates any combination of output frequencies from any input frequency using fourth-generation DSPLL and MultiSynth technologies.
• Features programmable jitter attenuation bandwidth ranging from 0.1 Hz to 4 kHz for optimized performance.
• Supports hitless input clock switching between fractionally related clocks and glitchless on-the-fly output frequency changes.
• Includes in-circuit programmable non-volatile memory to ensure known frequency configuration upon power-up.

Clock Generators, PLLs, Frequency Synthesizers Applications

• OTN muxponders and transponders
• 10/40/100 G networking line cards
• GbE/10 GbE/100 GbE Synchronous Ethernet (ITU-T G.8262)
• Carrier Ethernet switches
• SONET/SDH line cards

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific ordering suffix against the manufacturer's current documentation to confirm factory preprogramming details. Ensure the component matches the required RoHS-6 compliance and Pb-free status. Confirm that the serial interface configuration aligns with system requirements before finalizing procurement orders.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this model when applications require low-jitter generation up to 350 MHz with multiple configurable outputs. The device supports both integer and fractional synthesis modes. Consider the integrated loop filter and internal crystal loading capacitors to simplify PCB layout and reduce noise coupling risks compared to discrete solutions.

Clock Generators, PLLs, Frequency Synthesizers Part Context

This component belongs to the Si5345/44/42 Rev D family of jitter attenuating clock multipliers. The Si5345 variant specifically provides four inputs and ten outputs housed in a 9x9 mm 64-QFN package. It utilizes Skyworks' proprietary DSPLL and MultiSynth technologies for high-performance clock generation.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

Si5345A-D-GMR

Clock Generators, PLLs, Frequency Synthesizers FAQ

What are the supported input frequency ranges?

The device accepts differential input frequencies from 8 kHz to 750 MHz and LVCMOS input frequencies from 8 kHz to 250 MHz.

How does the device handle input clock failures?

It automatically enters holdover mode using stored historical frequency data if the selected input becomes invalid and no other valid inputs are available.

Is external crystal loading capacitance required?

No, the device includes internal XTAL loading capacitors, eliminating the need for external capacitors on the XA/XB pins.