SI5396A-A-GMR

Clock Generators, PLLs, Frequency Synthesizers Overview

The SI5396A-A-GMR is a dual DSPLL jitter attenuator clock multiplier from Skyworks Solutions, utilizing fourth-generation technology to generate any output frequency from any input frequency. It features two independent DSPLLs with four inputs and four outputs housed in a 44-QFN package. The device supports differential input frequencies from 8 kHz to 750 MHz and LVCMOS inputs up to 250 MHz. Output frequencies range from 100 Hz to 720 MHz for differential formats and up to 250 MHz for LVCMOS. It provides ultra-low phase jitter of 95 fs rms and includes programmable jitter attenuation bandwidths from 0.1 Hz to 4 kHz.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Dual DSPLL architecture enables synchronization to multiple time domains with independent operation
• Flexible crosspoint routing allows any input to connect to any output clock
• Enhanced hitless switching minimizes output phase transients during input clock changes
• Supports automatic free-run and holdover modes for system reliability

Clock Generators, PLLs, Frequency Synthesizers Applications

• OTN muxponders and transponders
• 10/40/100/400GbE systems
• Synchronous Ethernet (ITU-T G.8262)
• 10/25/100G Carrier Ethernet switches
• Broadcast video equipment

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific ordering suffix against the manufacturer's official documentation to confirm package type and reference configuration. Ensure compatibility with required serial interface protocols and voltage levels before integration. Cross-reference the datasheet revision date to confirm current specifications and compliance status.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this component when dual independent PLL paths are required for separate timing domains. Verify that the external crystal or oscillator reference meets the specified frequency range for optimal jitter performance. Confirm that the 44-QFN package dimensions fit the target PCB layout constraints.

Clock Generators, PLLs, Frequency Synthesizers Part Context

This part belongs to the Si5396 family, which offers dual DSPLL configurations. It serves as an upgrade path for legacy designs using Si5347/46 devices, providing drop-in compatibility while offering enhanced jitter attenuation and flexible frequency synthesis capabilities for high-performance networking applications.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

The Si5396A-A-GMR is designed as a drop-in replacement for the Si5347 and Si5346 series. Verify pinout compatibility and register mapping differences when migrating existing designs to ensure seamless integration without hardware modifications.